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GM71V16160C GM71VS16160CL
1,048,576 WORDS x 16 BIT CMOS DYNAMIC RAM
Description
The GM71V(S)16160C/CL is the new generation dynamic RAM organized 1,048,576 x 16 bit. GM71V(S)16160C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71V(S)16160C/CL offers Fast Page Mode as a high speed access mode. Multiplexed address inputs permit the GM71V(S)16160C/CL to be packaged in standard 400 mil 42pin plastic SOJ, and standard 400mil 44(50)pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment.
Features
* 1,048,576 Words x 16 Bit Organization * Fast Page Mode Capability * Single Power Supply (3.3V+/-0.3V) * Fast Access Time & Cycle Time
(Unit: ns)
tRAC tCAC
GM71V(S)16160C/CL-5 GM71V(S)16160C/CL-6 GM71V(S)16160C/CL-7 50 60 70 13 15 18
tRC
90 110 130
tPC
35 40 45
Pin Configuration 42 SOJ
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS A11 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
* Low Power Active : 396/360/324mW (MAX) Standby : 7.2mW (CMOS level : MAX) 0.54mW (L-version : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible *4096 Refresh Cycles/64ms * 4096 Refresh Cycles/128ms (L-version) * Self Refresh Operation (L-version) * Battery Back Up Operation (L-version) * 2 CAS byte Control
44(50) TSOP II
VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS NC NC WE RAS A11 A10 A0 A1 A2 A3 VCC
15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC
1 2 3 4 5 6 7 8 9 10 11
50 49 48 47 46 45 44 43 42 41 40
VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC
om .c 4u et he as at .d w w w
16 17 18 19 20 21
NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
(Top View)
Rev 0.1 / Apr'01
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GM71V16160C GM71VS16160CL
Pin Description
Pin
A0-A11 A0-A11 I/O0-I/O15 RAS UCAS, LCAS
Function
Address Inputs Refresh Address Inputs Data Input/ Data Output Row Address Strobe Column Address Strobe
Pin
WE OE VCC VSS NC
Function
Read/Write Enable Output Enable Power (+3.3V) Ground No Connection
Ordering Information
Type No.
GM71V(S)16160CJ/CLJ -5 GM71V(S)16160CJ/CLJ -6 GM71V(S)16160CJ/CLJ -7
Access Time
50ns 60ns 70ns
Package
400 Mil 42 Pin Plastic SOJ
GM71V(S)16160CT/CLT -5 GM71V(S)16160CT/CLT -6 GM71V(S)16160CT/CLT -7
50ns 60ns 70ns
400 Mil 44(50) Pin Plastic TSOP II
Absolute Maximum Ratings*
Symbol TA TSTG VIN/OUT VCC IOUT PD Parameter
Ambient Temperature under Bias Storage Temperature Voltage on any Pin Relative to VSS Supply Voltage Relative to VSS Short Circuit Output Current Power Dissipation
Rating
0 ~ 70 -55 ~ 125 -0.5 ~ Vcc+0.5 (<=4.6V(MAX)) -0.5 ~ 4.6 50 1.0
Unit
C C V V mA W
Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Rev 0.1 / Apr'01
GM71V16160C GM71VS16160CL
Recommended DC Operating Conditions (TA = 0 ~ +70C)
Symbol VCC VIH VIL Parameter
Supply Voltage Input High Voltage Input Low Voltage
Min
3.0 2.0 -0.3
Typ
3.3 -
Max
3.6 VCC + 0.3 0.8
Unit
V V V
Note: All voltage referred to Vss. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
Truth Table
RAS
H L L L L L L L L L L L L H to L H to L H to L L L
LCAS
D L H L L H L L H L L H L H L L H L
UCAS
D H L L H L L H L L H L L L H L H L
WE
D H H H L L L L L L H to L H to L H to L D D D D H
OE
D L L L D D D H H H L to H L to H L to H D D D D H
Output
Open Valid Valid Valid Open Open Open Undefined Undefined Undefined Valid Valid Valid Open Open Open Open Open
Operation
Standby Lower byte Upper byte Word Lower byte Upper byte Word Lower byte Upper byte Word Lower byte Upper byte Word Word Word Word Word CBR Refresh or Self Refresh (L-series) RAS-only Refresh cycle Read-modify -write cycle Delayed Write cycle Early write cycle Read cycle
Notes
1,3
1,3
1,2,3
1,2,3
1,3
1,3
1,3 1,3
Read cycle (Output disabled)
Notes: 1. H: High (inactive) L: Low(active) D: H or L 2. tWCS >= 0ns Early write cycle tWCS <= 0ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output High-Z control are done independently by each UCAS,LCAS. ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
Rev 0.1 / Apr'01
GM71V16160C GM71VS16160CL
DC Electrical Characteristics (VCC = 3.3V+/-0.3V, Vss = 0V, TA = 0 ~ 70C)
Symbol VOH VOL ICC1 Parameter
Output Level Output "H" Level Voltage (IOUT = -2mA) Output Level Output "L" Level Voltage (IOUT = 2mA) Operating Current Average Power Supply Operating Current (RAS, UCAS or LCAS Cycling: tRC = tRC min) Standby Current (TTL) Power Supply Standby Current (RAS, UCAS, LCAS = VIH, DOUT = High-Z) RAS Only Refresh Current Average Power Supply Current RAS Only Refresh Mode (tRC = tRC min) Fast Page Mode Current Average Power Supply Current Fast Page Mode (tPC = tPC min) Standby Current (CMOS) Power Supply Standby Current (RAS, UCAS or LCAS >= VCC - 0.2V, DOUT = High-Z) CAS-before-RAS Refresh Current (tRC = tRC min) 50ns 60ns 70ns 50ns 60ns 70ns 50ns 60ns 70ns 50ns 60ns 70ns
Min
2.4 0 -
Max
VCC 0.4 110 100 90 2 110 100 90 115 105 95 1 150 110 100 90 400
Unit
V V
Note
mA
1, 2
ICC2
mA
ICC3
mA
2
ICC4
mA
1, 3
ICC5
mA uA 5
ICC6
mA
ICC7 ICC8 ICC9 IL(I) IL(O)
Battery Back Up Operating Current (Standby with CBR Refresh) (tRC=31.3us, tRAS<=0.3us, DOUT=High-Z) Standby Current RAS = VIH UCAS, LCAS = VIL DOUT = Enable Self-Refresh Mode Current (RAS, UCAS or LCAS<=0.2V, DOUT=High-Z) Input Leakage Current Any Input (0V<=VIN<= 4.6V) Output Leakage Current (DOUT is Disabled, 0V<=VOUT<= 4.6V) ICC(max) is specified at the output open condition.
uA
4,5
-10 -10
5 250 10 10
mA uA uA uA
1 5
Note: 1. ICC depends on output load condition when the device is selected. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while UCAS and LCAS = VIH. 4. UCAS = L (<=0.2) and LCAS = L (<=0.2) while RAS = L (<=0.2). 5. L-version.
Rev 0.1 / Apr'01
GM71V16160C GM71VS16160CL
Capacitance (VCC = 3.3V+/-0.3V, TA = 25C)
Symbol CI1 CI2 CI/O Parameter
Input Capacitance (Address) Input Capacitance (Clocks) Output Capacitance (Data-In/Out)
Min
-
Max
5 7 7
Unit
pF pF pF
Note
1 1 1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. UCAS and LCAS = VIH to disable DOUT.
AC Characteristics (VCC = 3.3V+/-0.3V, TA = 0 ~ +70C, Note 1, 2, 18, 19, 20)
Test Conditions
Input rise and fall times : 5 ns Input timing reference levels : 0.8V, 2.0V Output timing reference levels : 0.8V, 2.0V Output load : 1TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol Parameter
Random Read or Write Cycle Time RAS Precharge Time CAS Precharge Time RAS Pulse Width CAS Pulse Width Row Address Set up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time RAS to CAS Delay Time RAS to Column Address Delay Time RAS Hold Time CAS Hold Time CAS to RAS Precharge Time OE to DIN Delay Time OE Delay Time from DIN CAS Delay Time from DIN Transition Time (Rise and Fall)
GM71V(S)16160 GM71V(S)16160 GM71V(S)16160 C/CL-6 C/CL-7 C/CL-5
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
Min Max Min Max Min Max
tRC tRP tCP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC tT
90 30 8
-
110 40 10
-
130 50 10
-
24
50 10,000 13 10,000 0 8 0 8 18 13 13 50 5 13 0 0 3 45 30 50
60 10,000 15 10,000 0 10 0 10 20 15 15 60 5 15 0 0 3 45 30 50
70 10,000 18 10,000 0 10 0 15 20 15 18 70 5 18 0 0 3 52 35 50
21 21 3 4
23 22 5 6 6 7
Rev 0.1 / Apr'01
GM71V16160C GM71VS16160CL
Read Cycle
Symbol Parameter
Access Time from RAS Access Time from CAS Access Time from Address Access Time from OE Read Command Setup Time Read Command Hold Time to CAS Read Command Hold Time to RAS Column Address to RAS Lead Time Column Address to CAS Lead Time CAS to Output in Low-Z Output Data Hold Time Output Data Hold Time from OE Output Buffer Turn-off Time Output Buffer Turn-off Time to OE CAS to DIN Delay Time
GM71V(S)16160 GM71V(S)16160 GM71V(S)16160 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
8,9 9,10,17 9,11,17 9,25
Min Max
Min Max Min Max 0 0 5 30 30 0 3 3 15 60 15 30 15 15 15 0 0 5 35 35 0 3 3 18 70 18 35 18 15 15 -
tRAC tCAC tAA tOAC tRCS tRCH tRRH tRAL tCAL tCLZ tOH tOHO tOFF tOEZ tCDD
0 0 5 25 25 0 3 3 13
50 13 25 13 13 13 -
12,22 12
13 13 5
Write Cycle
Symbol Parameter
Write Command Setup Time Write Command Hold Time Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time
GM71V(S)16160 GM71V(S)16160 GM71V(S)16160 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns ns ns ns ns ns
Note
14,21 21
Min Max Min Max Min Max
tWCS tWCH
0 8 8 13 13 0 8
-
0 10 10 15 15 0 10
-
0 15 10 18 18 0 15
-
tWP
tRWL tCWL tDS tDH
23 15,23 15,23
Rev 0.1 / Apr'01
GM71V16160C GM71VS16160CL
Read- Modify-Write Cycle
Symbol Parameter
Read-Modify-Write Cycle Time RAS to WE Delay Time CAS to WE Delay Time Column Address to WE Delay Time OE Hold Time from WE
GM71V(S)16160 GM71V(S)16160 GM71V(S)16160 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns ns ns ns
Note
Min Max Min Max Min Max
tRWC tRWD tCWD tAWD tOEH
131 73 36 48 13
-
155 85 40 55 15
-
181 98 46 63 18
-
14 14 14
Refresh Cycle
Symbol Parameter
CAS Setup Time (CAS-before-RAS Refresh Cycle) CAS Hold Time (CAS-before-RAS Refresh Cycle) RAS Precharge to CAS Hold Time
GM71V(S)16160 GM71V(S)16160 GM71V(S)16160 C/CL-5 C/CL-6 C/CL-7
Unit
Note
Min Max Min Max Min Max
tCSR tCHR tRPC
5 8 5
-
5 10 5
-
5 10 5
-
ns ns ns
21 22 21
Fast Page Mode Cycle
Symbol Parameter
Fast Page Mode Cycle Time Fast Page Mode RAS Pulse Width Access Time from CAS Precharge RAS Hold Time from CAS Precharge
GM71V(S)16160 GM71V(S)16160 GM71V(S)16160 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns ns ns
Note
Min Max Min Max Min Max
tPC tRASP tACP tRHCP
35 30
100,000
40 35
100,000
45 40
100,000
16 9,17,22
30 -
35 -
40 -
Fast Page Mode Read-Modify-Write Cycle
Symbol Parameter
Fast Page Mode Read-Modify-Write Cycle Time WE Delay Time from CAS Precharge
GM71V(S)16160 GM71V(S)16160 GM71V(S)16160 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns
Note
Min Max Min Max Min Max
tPRWC tCPW
76 53
-
85 60
-
96 68
-
14,22
Rev 0.1 / Apr'01
GM71V16160C GM71VS16160CL
Self Refresh Mode
Symbol Parameter
RAS Pulse Width(Self-Refresh) RAS Precharge Time(Self-Refresh) CAS Hold Time(Self-Refresh)
GM71VS16160 CL-5 GM71VS16160 CL-6 GM71VS16160 CL-7
Unit
us ns ns
Note
26
Min Max
Min Max Min Max 100 110 -50 100 130 -50 -
tRASS tRPS tCHS
100 90 -50
-
Notes: 1. AC measurements assume tT = 5ns. 2. An initial pause of 200us is required after power up followed by a minimum of eight initialization cycles(any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD(max)limit insures that tRAC(max)can be met, tRCD(max)is specified as a reference point only; if tRCD >= tRAD(max) + tAA(max) - tCAC(max), then access time is controlled exclusively by tCAC. 4. Operation with the tRAD(max) limit insures that tRAC(max)can be met, tRAD(max)is specified as a reference point only; if tRAD is greater than the specified tRAD(max)limit, then access time is controlled exclusively by tAA. 5. Either tODD or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH(min) and VIL(max). 8. Assumes that tRCD <= tRCD(max) and tRAD <= tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL load and 100pF. 10. Assumes that tRCD >= tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max). 11. Assumes that tRAD >= tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS >= tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle ; if tRWD >= tRWD(min), tCWD >=tCWD(min), and tAWD >= tAWD(min), or tCWD >= tCWD(min),tAWD >= tAWD(min) and tCPW >= tCPW(min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of data out (at access time)is indeterminate.
Rev 0.1 / Apr'01
GM71V16160C GM71VS16160CL
15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. tRASP defines RAS pulse width in fast page mode cycles. 17. Access time is determined by the longest among tAA,tCAC,and tACP. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH >= tCWL, the I/O pin will remain open circuit (high impedance); if tOEH< tCWL, invalid data will be out at each I/O. 19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 20. All the VCC and VSS pins shall be supplied with the same voltages. 21. tASC, tCAH, tRCS, tWCS,tWCH,tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS. 22. tCRP,tCHR, tRCH, tACP and tCPW are determined by the later rising edge of UCAS or LCAS. 23. tCWL, tDH,tDS and tCSH should be satisfied by both UCAS and LCAS. 24. tCP is determined by that time the both UCAS and LCAS are high. 25. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 26. Please do not use tRASS timing, 10us <= tRASS <=100us. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS >=100us, then RAS precharge time should use tRPS instead of tRP. 27. H or L (H: VIH(min) <= VIN <= VIH(max), L: VIL(min) <= VIN <= VIL(max))
Rev 0.1 / Apr'01
GM71V16160C GM71VS16160CL
Package Dimension
42pin SOJ
Unit: Inches (mm)
0.025(0.64) MIN 0.405(10.29) MAX 0.445(11.30) MAX 0.395(10.03) MIN 0.435(11.06) MIN 0.380(9.65) MAX 0.360(9.15) MIN
0~5 Deg
1.058(26.89) MAX 1.072(27.23) MAX
0.093(2.38) MIN
0.128(3.25) MIN 0.148(3.75) MAX 0.050(1.27) TYP 0.015(0.38) MIN 0.020(0.50) MAX 0.026(0.66) MIN 0.032(0.81) MAX
44(50)pin TSOP II
0.016(0.40) MIN 0.024(0.60) MAX
0.405(10.29) MAX
0.471(11.96) MAX
0.394(10.03) MIN
0.455(11.56) MIN
0.820(20.82) MIN 0.830(21.08) MAX 0.037(0.95) MIN 0.041(1.05) MAX 0.047(1.20) MAX 0.012(0.30) MIN 0.017(0.45) MAX 0.031(0.80) TYP 0.002(0.05) MIN 0.006(0.15) MAX
0.004(0.12) MIN 0.008(0.21) MAX
Rev 0.1 / Apr'01

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